drm/i915: Add fallback for CDCLK selection when min_cdclk is too high

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In cases where the requested minimum CDCLK exceeds all available
values for the current reference clock, the CDCLK selection logic
previously returned 0. This could result coverity division or
modulo by zero issue.
Introduce a fallback mechanism that returns platform's max_cdclk_freq
instead of 0.

v2: Update safe fallback value to max cdclk. (Ville)
v3: Update commit messgae (Mika)

Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20251017150526.781715-1-ramanaidu.naladala@intel.com

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Naladala Ramanaidu 2025-10-17 20:35:26 +05:30 • committed by Suraj Kandpal

parent 938c6c9be3

commit bbbfa70dfe

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/display/intel_cdclk.c

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