From bc1773bea9627eeccd6f035c285769ee9c590f9b Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Mon, 21 Sep 2026 15:16:44 -0400 Subject: [PATCH] drm/amd/display: Update default clocks for DCN60 lite3 variant [Why] These are important for getting correct DP and audio output. The wrong pixel clock will be used otherwise. [How] Update the default clocks for the DCN60 lite3 variant. Signed-off-by: Nicholas Kazlauskas Signed-off-by: Fangzhi Zuo Reviewed-by: Nicholas Kazlauskas Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c index d0036fa1b7e5..d8a0a482d984 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c @@ -1804,6 +1804,7 @@ struct clk_mgr_internal *dcn60_clk_mgr_construct( { struct dcn60_clk_mgr *clk_mgr60 = kzalloc_obj(struct dcn60_clk_mgr); struct clk_mgr_internal *clk_mgr; + bool variant_clocks = ASICREV_IS_DCN6_VARIANT_LITE3(ctx->asic_id.hw_internal_rev); if (!clk_mgr60) return NULL; @@ -1828,14 +1829,14 @@ struct clk_mgr_internal *dcn60_clk_mgr_construct( * dcn60_dump_clk_registers from 4 * dentist_vco_freq_khz / * dprefclk DID divider */ - clk_mgr->base.dprefclk_khz = 720000; + clk_mgr->base.dprefclk_khz = variant_clocks ? 607407 : 720000; /* integer part is now VCO frequency in kHz */ clk_mgr->base.dentist_vco_freq_khz = dcn60_get_vco_frequency_from_reg(clk_mgr); /* in case we don't get a value from the register, use default */ if (clk_mgr->base.dentist_vco_freq_khz == 0) - clk_mgr->base.dentist_vco_freq_khz = 4500000; + clk_mgr->base.dentist_vco_freq_khz = variant_clocks ? 4100000 : 4500000; clk_mgr->dfs_bypass_enabled = false;