drm/i915/icl: toggle PHY clock gating around link training

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The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
section says that PHY clock gating should be disabled before starting
voltage swing programming, then enabled after any link training is
complete.

v2: Simple rebase.

Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180725002813.6938-6-paulo.r.zanoni@intel.com

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This commit is contained in:

Paulo Zanoni 2018-07-24 17:28:13 -07:00

parent 340a44bef2

commit bc334d914e

4 changed files with 91 additions and 0 deletions

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20

drivers/gpu/drm/i915/i915_reg.h

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3

drivers/gpu/drm/i915/intel_ddi.c

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66

drivers/gpu/drm/i915/intel_dp.c

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2

drivers/gpu/drm/i915/intel_drv.h

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