drm/i915/execlists: Unify CSB access pointers

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Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce the CSB access to a set of read/write/buffer pointers and
treat the various paths identically and not worry about forcewake.
(Forcewake is nightmare for worstcase latency, and we want to process
this all with irqsoff -- no latency allowed!)

v2: Comments, comments, comments. Well, 2 bonus comments.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180628201211.13837-5-chris@chris-wilson.co.uk

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This commit is contained in:

Chris Wilson 2018-06-28 21:12:07 +01:00

parent 8ea397fa70

commit bc4237ec8d

3 changed files with 82 additions and 86 deletions

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12

drivers/gpu/drm/i915/intel_engine_cs.c

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133

drivers/gpu/drm/i915/intel_lrc.c

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23

drivers/gpu/drm/i915/intel_ringbuffer.h

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