perf vendor events intel: Update tigerlake events/metrics

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Update tigerlake events to v1.12 including the new events
MEM_LOAD_MISC_RETIRED.UC and SQ_MISC.BUS_LOCK. Metrics are updated to
make TMA info metric names synchronized. Events and metrics were
generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230517173805.602113-14-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

...

This commit is contained in:

Ian Rogers 2023-05-17 10:38:02 -07:00 • committed by Arnaldo Carvalho de Melo

parent d97b82aead

commit bc4e41210e

4 changed files with 505 additions and 486 deletions

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2

tools/perf/pmu-events/arch/x86/mapfile.csv

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1 Family-model Version Filename EventType 29 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v56 skylake core 30 GenuineIntel-6-55-[01234] v1.30 skylakex core 31 GenuineIntel-6-86 v1.21 snowridgex core 32 GenuineIntel-6-8[CD] v1.10 v1.12 tigerlake core 33 GenuineIntel-6-2C v4 westmereep-dp core 34 GenuineIntel-6-25 v3 westmereep-sp core 35 GenuineIntel-6-2F v3 westmereex core

18

tools/perf/pmu-events/arch/x86/tigerlake/cache.json

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1

tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json

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1354

tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json

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