clk: tegra: Init cfg structure in _get_pll_mnp

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Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.

Based on work by  Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Peter De Schrijver 2017-07-25 13:34:06 +03:00 • committed by Stephen Boyd

parent e34e69cc86

commit bc7b34a2fb

1 changed files with 2 additions and 0 deletions

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drivers/clk/tegra/clk-pll.c

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