ASoC: Intel: bytcr_rt5640: Configure PLL1 before using it

Browse source

When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL
registers have not been setup yet and we effectively have an invalid clock
configuration until byt_rt5640_aif1_hw_params() gets called.

Add a new byt_rt5640_prepare_and_enable_pll1() helper and use that from
both platform_clock_control() and byt_rt5640_aif1_hw_params() to fix this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

...

This commit is contained in:

Hans de Goede 2018-05-08 17:35:53 +02:00 • committed by Mark Brown

parent b16188a20f

commit bcd9a325f0

No known key found for this signature in database

GPG key ID: 24D68B725D5487D0

1 changed files with 49 additions and 51 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

100

sound/soc/intel/boards/bytcr_rt5640.c

View file