clk: imx: imx8mq: fix sys3_pll_out_sels

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It is not correct that sys3_pll_out use sys2_pll1_ref_sel as parent.

According to the current imx_clk_sccg_pll design, it uses both
bypass1/2, however set bypass2 as 1 is not correct, because it will
make sys[x]_pll_out use wrong parent and might access wrong registers.

So correct bypass2 to 0 and fix sys3_pll_out_sels.

Fixes: e9dda4af68 ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Peng Fan 2019-10-28 03:08:34 +00:00 • committed by Shawn Guo

parent 72b2429d40

commit bceed71ba1

1 changed files with 2 additions and 2 deletions

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drivers/clk/imx/clk-imx8mq.c

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