dt-bindings: clock: Add StarFive JH7110 PLL clock generator

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Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Xingyu Wu 2023-07-17 10:30:34 +08:00 • committed by Conor Dooley

parent 06c2afb862

commit bd348ca24d

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46

Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

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6

include/dt-bindings/clock/starfive,jh7110-crg.h

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