sfc: support pio mapping based on cxl

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A PIO buffer is a region of device memory to which the driver can write a
packet for TX, with the device handling the transmit doorbell without
requiring a DMA for getting the packet data, which helps reducing latency
in certain exchanges. With CXL mem protocol this latency can be lowered
further.

With a device supporting CXL and successfully initialised, use the cxl
region to map the memory range and use this mapping for PIO buffers.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
Link: https://patch.msgid.link/20260630151346.31201-6-alejandro.lucero-palau@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

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This commit is contained in:

Alejandro Lucero 2026-06-30 16:13:46 +01:00 • committed by Dave Jiang

parent 0418860ef2

commit bd6550bcdb

4 changed files with 40 additions and 7 deletions

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41

drivers/net/ethernet/sfc/ef10.c

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1

drivers/net/ethernet/sfc/efx_cxl.c

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2

drivers/net/ethernet/sfc/net_driver.h

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3

drivers/net/ethernet/sfc/nic.h

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