clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries

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Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2022-04-25 10:52:40 +01:00 • committed by Geert Uytterhoeven

parent a9391e0190

commit be5b5fcbc7

1 changed files with 20 additions and 0 deletions

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drivers/clk/renesas/r9a07g043-cpg.c

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