From bed6347ae41b03bb80786b623c648cf221d7ed43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 26 Aug 2026 16:40:20 +0300 Subject: [PATCH] drm/i915/cdclk: Don't bail if pcode post nofify fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We already changed the actual cdclk frequency by the time we do the pcode post notify. So skipping the subsequent readout is plain wrong. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260826134033.13976-2-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 279006f7b881..0c2d80edc5ab 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2328,12 +2328,10 @@ static void bxt_set_cdclk(struct intel_display *display, HSW_PCODE_DE_WRITE_FREQ_REQ, cdclk_config->voltage_level, 2); } - if (ret) { + if (ret) drm_err(display->drm, "PCode CDCLK freq set failed, (err %d, freq %d)\n", ret, cdclk); - return; - } intel_update_cdclk(display);