clk: renesas: r9a09g056-cpg: Add clock and reset entries for GBETH0/1

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Add clock and reset entries for GBETH instances. Include core clocks for
PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
used as clock sources for the GBETH IP.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-05-13 16:46:31 +01:00 • committed by Geert Uytterhoeven

parent 598b2a0670

commit bfb0bc6bdf

1 changed files with 66 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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