iommu/omap: Use DMA-API for performing cache flushes

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The OMAP IOMMU driver was using ARM assembly code directly for
flushing the MMU page table entries from the caches. This caused
MMU faults on OMAP4 (Cortex-A9 based SoCs) as L2 caches were not
handled due to the presence of a PL310 L2 Cache Controller. These
faults were however not seen on OMAP5/DRA7 SoCs (Cortex-A15 based
SoCs).

The OMAP IOMMU driver is adapted to use the DMA Streaming API
instead now to flush the page table/directory table entries from
the CPU caches. This ensures that the devices always see the
updated page table entries. The outer caches are now addressed
automatically with the usage of the DMA API.

Signed-off-by: Josue Albarran <j-albarran@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

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This commit is contained in:

Josue Albarran 2017-07-28 15:49:14 -05:00 • committed by Joerg Roedel

parent 159d3e35da

commit bfee0cf0ee

2 changed files with 80 additions and 44 deletions

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125

drivers/iommu/omap-iommu.c

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1

drivers/iommu/omap-iommu.h

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