clk: tegra: Don't enable already enabled PLLs

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Initially Common Clock Framework isn't aware of the clock-enable status,
this results in enabling of clocks that were enabled by bootloader. This
is not a big deal for a regular clock-gates, but for PLL's it may have
some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
clock) may result in extra long period of PLL re-locking.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Dmitry Osipenko 2019-04-19 14:42:26 +03:00 • committed by Stephen Boyd

parent 9e98c678c2

commit bff1cef5f2

1 changed files with 37 additions and 13 deletions

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drivers/clk/tegra/clk-pll.c

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