drm/amd/display: update dpp dto phase and modulo.

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[Why & How]
Program modulo with ref dpp clk Mhz/10.
Program phase with pipe dpp clk Mhz /10.
DMUB FW could use these value to determine optimization clk
for PSR power saving.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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This commit is contained in:

Yongqiang Sun 2020-10-26 12:33:24 -04:00 • committed by Alex Deucher

parent c616090023

commit c07cbc1f04

5 changed files with 166 additions and 6 deletions

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6

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

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2

drivers/gpu/drm/amd/display/dc/dcn21/Makefile

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125

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c

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36

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.h

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3

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

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