clk: socfpga: stratix10: fix rate calculation for pll clocks

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The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db73 ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Dinh Nguyen 2018-12-17 18:06:14 -06:00 • committed by Stephen Boyd

parent 83b4c14796

commit c0a636e4cc

1 changed files with 1 additions and 1 deletions

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drivers/clk/socfpga/clk-pll-s10.c

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