ARM: 9057/1: cache-v7: add missing ISB after cache level selection

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A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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Ard Biesheuvel 2021-02-11 09:19:46 +01:00 • committed by Russell King

parent c4e792d1ac

commit c0e50736e8

1 changed files with 4 additions and 3 deletions

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arch/arm/mm/cache-v7.S

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