drm/amd/pm: Disable MMIO access during SMU Mode 1 reset

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[ Upstream commit 0de604d035 ]

During Mode 1 reset, the ASIC undergoes a reset cycle and becomes
temporarily inaccessible via PCIe. Any attempt to access MMIO registers
during this window (e.g., from interrupt handlers or other driver threads)
can result in uncompleted PCIe transactions, leading to NMI panics or
system hangs.

To prevent this, set the `no_hw_access` flag to true immediately after
triggering the reset. This signals other driver components to skip
register accesses while the device is offline.

A memory barrier `smp_mb()` is added to ensure the flag update is
globally visible to all cores before the driver enters the sleep/wait
state.

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 7edb503fe4)
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Perry Yuan 2025-12-25 16:43:49 +08:00 • committed by Greg Kroah-Hartman

parent ff8a020151

commit c1853ebbec

3 changed files with 16 additions and 3 deletions

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3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

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7

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

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9

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

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