drm/i915: Hook up display fault interrupts for VLV/CHV

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Hook up the display fault irq handlers for VLV/CHV.

Unfortunately the actual hardware doesn't agree with the
spec on how DPINVGTT should behave. The docs claim that
the status bits can be cleared by writing '1' to them,
but in reality there doesn't seem to be any way to clear
them. So we must disable and ignore any fault we've already
seen in the past. The entire register does reset when
the display power well goes down, so we can just always
re-enable all the bits in irq postinstall without having
to track the state beyond that.

v2: Use intel_display instead of dev_priv
    Move xe gen2_error_{init,reset}() out

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250217070047.953-9-ville.syrjala@linux.intel.com

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This commit is contained in:

Ville Syrjälä 2025-02-17 09:00:47 +02:00

parent b6cfae8d9c

commit c19f5a0341

4 changed files with 158 additions and 1 deletions

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132

drivers/gpu/drm/i915/display/intel_display_irq.c

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3

drivers/gpu/drm/i915/display/intel_display_irq.h

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14

drivers/gpu/drm/i915/i915_irq.c

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10

drivers/gpu/drm/i915/i915_reg.h

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