drm/amdgpu: Correct se_num and reg_inst for gfx v9_4_3 ras counters

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gfx_v9_4_3_ue|ce_reg_list is an array per gfx core instance
correct the settings of se_num and reg_inst for some of
gfx ras counters so all the available register instances
can be polled for ras status.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Hawking Zhang 2023-09-06 17:56:20 +08:00 • committed by Alex Deucher

parent 1b8e56b994

commit c2c23a10f1

1 changed files with 20 additions and 20 deletions

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drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

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