ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case

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The bit 10 in TX_DPTH_CTRL register controls the TX clock rate.
If this bit is set, TX datapath clock should be = 2* TX bit rate.
If this bit is not set, TX datapath clock should be 10* TX bit rate.

As the spdif only case, we always use 2 * TX bit clock, so
this bit need to be set.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1700617373-6472-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Shengjiu Wang 2023-11-22 09:42:53 +08:00 • committed by Mark Brown

parent 14e8442e07

commit c33fd11042

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sound/soc/fsl/fsl_xcvr.c

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