ASoC: amd: acp: add ZSC control register programming sequence

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Add ZSC Control register programming sequence for ACP D0 and D3 state
transitions for ACP7.0 onwards. This will allow ACP to enter low power
state when ACP enters D3 state. When ACP enters D0 State, ZSC control
should be disabled.

Tested-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20240807085154.1987681-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Vijendar Mukunda 2024-08-07 14:21:48 +05:30 • committed by Mark Brown

parent 20288905e1

commit c35fad6f7e

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5

sound/soc/amd/acp/acp-legacy-common.c

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2

sound/soc/amd/acp/amd.h

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