cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation

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RISC-V's implementation of init_of_cache_level() is following
the Devicetree Specification v0.3 regarding caches, cf.:
- s3.7.3 'Internal (L1) Cache Properties'
- s3.8 'Multi-level and Shared Cache Nodes'

Allow reusing the implementation by moving it.

Also make 'levels', 'leaves' and 'level' unsigned int.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

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Pierre Gondois 2023-01-04 19:30:24 +01:00 • committed by Sudeep Holla

parent 1b929c02af

commit c3719bd9ee

3 changed files with 46 additions and 38 deletions

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39

arch/riscv/kernel/cacheinfo.c

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44

drivers/base/cacheinfo.c

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1

include/linux/cacheinfo.h

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