net: dsa: mt7530: setup core clock even in TRGMII mode

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A recent change to MIPS ralink reset logic made it so mt7530 actually
resets the switch on platforms such as mt7621 (where bit 2 is the reset
line for the switch). That exposed an issue where the switch would not
function properly in TRGMII mode after a reset.

Reconfigure core clock in TRGMII mode to fix the issue.

Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.

Fixes: 3f9ef7785a ("MIPS: ralink: manage low reset lines")
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Ilya Lipnitskiy 2021-03-12 00:07:03 -08:00 • committed by David S. Miller

parent 2e5de7e0c8

commit c3b8e07909

1 changed files with 25 additions and 27 deletions

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drivers/net/dsa/mt7530.c

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