drm/nouveau/mc/tu102: Fix MMU fault interrupts on Turing

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Turing reports MMU fault interrupts via new top level interrupt
registers. The old PMC MMU interrupt vector is not used by the HW. This
means we can remap the new top-level MMU interrupt to the exisiting PMC
MMU bit which simplifies the implementation until all interrupts are
moved over to using the new top level registers.

Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

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Alistair Popple 2020-10-30 13:36:41 +11:00 • committed by Ben Skeggs

parent 36dc1777de

commit c3cc12eaf5

2 changed files with 122 additions and 6 deletions

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21

drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c

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107

drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c

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