x86/apic: Enable Secure AVIC in the control MSR

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With all the pieces in place now, enable Secure AVIC in the Secure AVIC
Control MSR. Any access to x2APIC MSRs are emulated by the hypervisor
before Secure AVIC is enabled in the control MSR.  Post Secure AVIC
enablement, all x2APIC MSR accesses (whether accelerated by AVIC
hardware or trapped as a #VC exception) operate on the vCPU's APIC
backing page.

Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828112126.209028-1-Neeraj.Upadhyay@amd.com

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This commit is contained in:

Neeraj Upadhyay 2025-08-28 16:51:26 +05:30 • committed by Borislav Petkov (AMD)

parent c8018325dd

commit c4074ab87f

2 changed files with 4 additions and 1 deletions

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2

arch/x86/include/asm/msr-index.h

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3

arch/x86/kernel/apic/x2apic_savic.c

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