PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS

Browse source

During L1SS, gate the Master clock supplied to the MHI bus to save power.

Link: https://lore.kernel.org/r/20220914075350.7992-7-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

...

This commit is contained in:

Manivannan Sadhasivam 2022-09-14 13:23:44 +05:30 • committed by Lorenzo Pieralisi

parent 6dbba2b53c

commit c457ac029e

1 changed files with 9 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

9

drivers/pci/controller/dwc/pcie-qcom-ep.c

View file