MIPS: math-emu: Implement the FCCR, FEXR and FENR registers

Browse source

Implement the FCCR, FEXR and FENR "shadow" FPU registers for the
architecture levels that include them, for the CFC1 and CTC1
instructions in the full emulation mode.

For completeness add macros for the CP1 UFR and UNFR registers too, no
actual implementation though.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

...

This commit is contained in:

Maciej W. Rozycki 2015-04-03 23:27:33 +01:00 • committed by Ralf Baechle

parent f684362689

commit c491cfa2ca

2 changed files with 148 additions and 27 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

69

arch/mips/include/asm/mipsregs.h

View file

106

arch/mips/math-emu/cp1emu.c

View file