ARM: l2c: ux500: remove cache size override

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The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Russell King 2014-03-19 01:22:05 +00:00

parent 6716173347

commit c4a202c8ae

1 changed files with 2 additions and 13 deletions

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arch/arm/mach-ux500/cache-l2x0.c

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