perf vendor events intel: Update tigerlake events to v1.15

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Update alderlake events to v1.15 released in:
282a6951fd

Documentation fixes, removal of TOPDOWN.BR_MISPREDICT_SLOTS,
deprecation of UNC_ARB_DAT_REQUESTS.RD, UNC_ARB_DAT_REQUESTS.RD and
UNC_ARB_IFA_OCCUPANCY.ALL.

Event json automatically generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240214011820.644458-13-irogers@google.com

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This commit is contained in:

Ian Rogers 2024-02-13 17:18:01 -08:00 • committed by Namhyung Kim

parent c31d718ca2

commit c4bb31c7b0

4 changed files with 5 additions and 11 deletions

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2

tools/perf/pmu-events/arch/x86/mapfile.csv

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1 Family-model Version Filename EventType 32 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v58 skylake core 33 GenuineIntel-6-55-[01234] v1.32 skylakex core 34 GenuineIntel-6-86 v1.21 snowridgex core 35 GenuineIntel-6-8[CD] v1.13 v1.15 tigerlake core 36 GenuineIntel-6-2C v5 westmereep-dp core 37 GenuineIntel-6-25 v4 westmereep-sp core 38 GenuineIntel-6-2F v4 westmereex core

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tools/perf/pmu-events/arch/x86/tigerlake/other.json

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tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json

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tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json

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