RISC-V cache drivers for v6.18

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sifive:
 Reduce the number of fences issued while flushing. Samuel reports that
 this is approximately a 15% speed-up.
 
 ax45mp:
 Fix the binding so that it permits the cache-sets setting used by the
 recently added QiLai SoC.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

RISC-V cache drivers for v6.18

sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.

ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  cache: sifive_ccache: Optimize cache flushes
  dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

Link: https://lore.kernel.org/r/20250924-relenting-aqua-a4a93b89809e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

...

This commit is contained in:

Arnd Bergmann 2025-09-24 23:17:20 +02:00

parent a53811fb37 941327ca5d

commit c4ebd66128

2 changed files with 9 additions and 5 deletions

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6

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml vendored

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8

drivers/cache/sifive_ccache.c vendored

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