arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay

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The Agilex5 SoC provides RGMII TX/RX clock delay compensation through
its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the
MAC driver to additionally insert internal TX/RX delays, resulting in
double delay being applied and causing Ethernet link timing issues.

Change phy-mode to "rgmii" across all Agilex5 device tree files to
reflect that the clock delay is already handled by the hardware and
no additional software-inserted delay is required. Add an inline comment
to satisfy checkpatch and document the hardware-provided delay.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

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Nazim Amirul 2026-05-06 20:32:02 -07:00 • committed by Dinh Nguyen

parent 90d083b05f

commit c5637e5ceb

4 changed files with 4 additions and 4 deletions

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arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

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arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts

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arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts

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arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts

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