drm/i915: Accurately initialize fifo underrun state on gmch platforms

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We don't have hardware based disable bits on gmch platforms, so need
to block spurious underrun reports in software. Which means that we
_must_ start out with fifo underrun reporting disabled everywhere.

This is in big contrast to ilk/hsw/cpt where there's only _one_
disable bit for all platforms and hence we must allow underrun
reporting on disabled pipes. Otherwise nothing really works,
especially the CRC support since that's key'ed off the same irq
disable bit.

This allows us to ditch the fifo underrun reporting hack from the vlv
runtime pm code and unexport the internal function from i915_irq.c
again. Yay!

v2: Keep the display irq disabling, spotted by Imre.

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Daniel Vetter 2014-05-14 15:40:34 +02:00

parent fd68e2379b

commit c5ab3bc07e

4 changed files with 10 additions and 11 deletions

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4

drivers/gpu/drm/i915/i915_irq.c

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9

drivers/gpu/drm/i915/intel_display.c

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2

drivers/gpu/drm/i915/intel_drv.h

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6

drivers/gpu/drm/i915/intel_pm.c

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