drm/i915: More PVC+DG2 workarounds

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A new PVC+DG2 workaround has appeared recently:
 - Wa_16015675438

And a couple existing DG2 workarounds have been extended to PVC:
 - Wa_14015795083
 - Wa_18018781329

Note that Wa_16015675438 asks us to program a register that is in the
0x2xxx range typically associated with the RCS engine, even though PVC
does not have an RCS.  By default the GuC will think we've made a
mistake and throw an exception when it sees this register on a CCS
engine's save/restore list, so we need to pass an extra GuC control flag
to tell it that this is expected and not a problem.

Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220608005108.3717895-1-matthew.d.roper@intel.com

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This commit is contained in:

Matt Roper 2022-06-07 17:51:08 -07:00

parent 5821a0bbb4

commit c5cb0002d1

4 changed files with 23 additions and 7 deletions

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1

drivers/gpu/drm/i915/gt/intel_gt_regs.h

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24

drivers/gpu/drm/i915/gt/intel_workarounds.c

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4

drivers/gpu/drm/i915/gt/uc/intel_guc.c

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1

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

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