drm/omap: Implement workaround for DRA7 errata ID:i932

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Description of DRA7 Errata i932:

In rare circumstances DPLL_VIDEO1 and DPLL_VIDEO2 PLL's may not lock on
the first attempt during DSS initialization. When this occurs, a
subsequent attempt to relock the PLL will result in PLL successfully
locking.

This patch does the following as per the errata recommendation:

- retries locking the PLL upto 20 times.

- The time to wait for a PLL lock set to 1000 REFCLK cycles. We use
usleep_range to wait for 1000 REFCLK cycles in the us range. This tight
constraint is imposed as a lock later than 1000 REFCLK cycles may have
high jitter.

- Criteria for PLL lock is extended from check on just the PLL_LOCK bit
to check on 6 PLL_STATUS bits.

Silicon Versions Impacted:
DRA71, DRA72, DRA74, DRA76 - All silicon revisions
AM57x - All silicon revisions

OMAP4/5 are not impacted by this errata

Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
[tomi.valkeinen@ti.com: ported to v4.14]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

...

This commit is contained in:

Venkateswara Rao Mandela 2018-01-24 16:15:09 +05:30 • committed by Tomi Valkeinen

parent 6ada132864

commit c618a3a93b

3 changed files with 67 additions and 10 deletions

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3

drivers/gpu/drm/omapdrm/dss/dss.h

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73

drivers/gpu/drm/omapdrm/dss/pll.c

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1

drivers/gpu/drm/omapdrm/dss/video-pll.c

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