mlxsw: spectrum: Allocate LAG table when in SW LAG mode

Browse source

In this patch, if the LAG mode is SW, allocate the LAG table and configure
SGCR to indicate where it was allocated.

We use the default "DDD" (for dynamic data duplication) layout of the LAG
table. In the DDD mode, the membership information for each LAG is copied
in 8 PGT entries. This is done for performance reasons. The LAG table then
needs to be allocated on an address aligned to 8. Deal with this by
moving the LAG init ahead so that the LAG table is allocated at address 0.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

...

This commit is contained in:

Petr Machata 2023-10-19 12:27:19 +02:00 • committed by David S. Miller

parent 8c893abd64

commit c678972580

2 changed files with 83 additions and 11 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

93

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

View file

1

drivers/net/ethernet/mellanox/mlxsw/spectrum.h

View file