clk: stm32mp1: add PLL clocks

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STMP32MP1 has 4 PLLs.
PLL supports integer and fractional mode.
Each PLL has 3 output dividers (p, q, r)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

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Gabriel Fernandez 2018-03-08 17:53:58 +01:00 • committed by Michael Turquette

parent dc32eaac49

commit c6cf4d3248

1 changed files with 209 additions and 0 deletions

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drivers/clk/clk-stm32mp1.c

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