Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"

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Restore PIPE_CONTROL once again just for Ironlake, as it appears that
MI_USER_INTERRUPT does not have the same coherency guarantees, that is
on Ironlake the interrupt following a GPU write is not guaranteed to
arrive after the write is coherent from the CPU, as it does on the
other generations.

Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reported-by: Shuang He <shuang.he@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

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This commit is contained in:

Chris Wilson 2010-12-15 09:56:50 +00:00

parent 1b894b5924

commit c6df541c00

2 changed files with 162 additions and 3 deletions

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3

drivers/gpu/drm/i915/i915_irq.c

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162

drivers/gpu/drm/i915/intel_ringbuffer.c

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