ath9k_hw: change the way we initialize the pll for ar9271

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We adjust the core clock for ar9271 to 117 MHz; this also
requires us to adjust the baud divider based on the targetted
baud rate.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

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Luis R. Rodriguez 2009-10-19 02:33:34 -04:00 • committed by John W. Linville

parent 8564328d85

commit c75724d174

2 changed files with 39 additions and 0 deletions

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36

drivers/net/wireless/ath/ath9k/hw.c

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3

drivers/net/wireless/ath/ath9k/reg.h

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