drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

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In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw

v2: Add LRI commands to set/reset bit that invalidates coherent lines,
update WA to include programming restrictions and exclude CHV as
it is not required (Ville)

v3: Avoid unnecessary read when it can be done by reading register once (Chris).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Arun Siluvery 2015-06-19 18:37:13 +01:00 • committed by Daniel Vetter

parent 7ad00d1ac1

commit c82435bbe5

2 changed files with 25 additions and 0 deletions

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2

drivers/gpu/drm/i915/i915_reg.h

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23

drivers/gpu/drm/i915/intel_lrc.c

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