perf/x86/intel: Add core PMU support for Novalake

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This patch enables core PMU support for Novalake, covering both P-core
and E-core. It includes Arctic Wolf-specific counters and PEBS
constraints, and the model-specific OMR extra registers table.

Since Coyote Cove shares the same PMU capabilities as Panther Cove, the
existing Panther Cove PMU enabling functions are reused for Coyote Cove.

For detailed information about counter constraints, please refer to
section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260114011750.350569-6-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-01-14 09:17:48 +08:00 • committed by Peter Zijlstra

parent 7cd264d197

commit c847a208f4

3 changed files with 112 additions and 0 deletions

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99

arch/x86/events/intel/core.c

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11

arch/x86/events/intel/ds.c

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2

arch/x86/events/perf_event.h

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