x86/mm: Cap flush_tlb_info alignment at 64 bytes

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A stack allocated flush_tlb_info should keep cacheline alignment to avoid
the regression that motivated the per-CPU storage, but using
SMP_CACHE_BYTES directly can make the stack frame grow excessively on
configurations with large cache lines. This was addressed by
commit 780e0106d4 ("x86/mm/tlb: Revert "x86/mm: Align TLB
invalidation info""), where the stack consumption reached 320 bytes.

Add FLUSH_TLB_INFO_ALIGN and cap the type alignment at 64 bytes. The
existing per-CPU flush_tlb_info instance remains
DEFINE_PER_CPU_SHARED_ALIGNED(), so its per-CPU shared-cacheline
alignment is unchanged.

This prepares for moving flush_tlb_info back to stack storage without
reintroducing the old large-cacheline stack usage problem.

Signed-off-by: Chuyi Zhou <zhouchuyi@bytedance.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Link: https://patch.msgid.link/20260709122933.4021501-12-zhouchuyi@bytedance.com

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Chuyi Zhou 2026-07-09 20:29:30 +08:00 • committed by Thomas Gleixner

parent 33c179b502

commit c86f522bb5

1 changed files with 8 additions and 1 deletions

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arch/x86/include/asm/tlbflush.h

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