ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som

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The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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Daniel Schultz 2018-03-05 13:45:11 +01:00 • committed by Heiko Stuebner

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commit c887f5b021

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arch/arm/boot/dts/rk3288-phycore-som.dtsi

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