clk: imx: pfdv2: determine best parent rate

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pfdv2 is only used in i.MX7ULP. To get best pfd output, the i.MX7ULP
Datasheet defines two best PLL rate and pfd frac.

Per Datasheel
All PLLs on i.MX 7ULP either have VCO base frequency of
480 MHz or 528 MHz. So when determine best rate, we also
determine best parent rate which could match the requirement.

For some reason the current parent might not be 480MHz or 528MHz,
so we still take current parent rate as a choice.

And we also enable flag CLK_SET_RATE_PARENT to let parent rate
to be configured.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Peng Fan 2020-02-19 15:59:48 +08:00 • committed by Shawn Guo

parent 8ffe9c7bb9

commit c88a4c797a

1 changed files with 33 additions and 17 deletions

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drivers/clk/imx/clk-pfdv2.c

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