clk: renesas: Add support for RZ/G2UL SoC

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The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.

This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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This commit is contained in:

Biju Das 2022-04-12 17:13:12 +01:00 • committed by Geert Uytterhoeven

parent 948f592433

commit c8b088224c

5 changed files with 171 additions and 1 deletions

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7

drivers/clk/renesas/Kconfig

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1

drivers/clk/renesas/Makefile

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157

drivers/clk/renesas/r9a07g043-cpg.c

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6

drivers/clk/renesas/rzg2l-cpg.c

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1

drivers/clk/renesas/rzg2l-cpg.h

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