From ea34dd0f029f4a30c055ddb6daaf7a6f3bee21ed Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 8 Oct 2024 11:14:20 +0200 Subject: [PATCH 01/34] arm64: dts: renesas: r8a774c0: Re-add voltages to OPP table When CONFIG_ENERGY_MODEL=y: cpu cpu0: EM: invalid perf. state: -22 When removing the (incorrect) voltages from the Operating Points Parameters tables, it was assumed they were optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. This assumption turned out to be incorrect, causing the reported error message. Fix this by re-adding the (correct) voltages. Note that because all voltages are identical, all operating points are considered to have the same efficiency, and the energy model always picks the one with the highest clock rate. Reported-by: Renesas Test Team via Kuninori Morimoto Fixes: 554edc3e9239bb81 ("arm64: dts: renesas: r8a774c0: Remove bogus voltages from OPP table") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/2046da75f3db95b62f86c0482063c4d04c2b47d5.1728377971.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 7655d5e3a034..522e20924e94 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -47,16 +47,20 @@ cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; opp-suspend; }; From c193f877770291f30d1e00bc6f2bb0757fe7a532 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 8 Oct 2024 11:14:21 +0200 Subject: [PATCH 02/34] arm64: dts: renesas: r8a77990: Re-add voltages to OPP table When CONFIG_ENERGY_MODEL=y: cpu cpu0: EM: invalid perf. state: -22 When removing the (incorrect) voltages from the Operating Points Parameters tables, it was assumed they were optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. This assumption turned out to be incorrect, causing the reported error message. Fix this by re-adding the (correct) voltages. Note that because all voltages are identical, all operating points are considered to have the same efficiency, and the energy model always picks the one with the highest clock rate. Reported-by: Renesas Test Team via Kuninori Morimoto Fixes: fb76b0fae3ca8803 ("arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP table") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/80890bc244670bc3e8d6fc89fb2c3cb23e7025f5.1728377971.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 233af3081e84..50fbf7251665 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -47,16 +47,20 @@ cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; opp-suspend; }; From 51786c8b47edfce3cee6eef9c8a62a035f9fbead Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 7 Jan 2025 17:01:26 +0100 Subject: [PATCH 03/34] arm64: dts: renesas: r8a779h0: Remove #address- and #size-cells from AVB[0-2] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When describing the PHYs connected to AVB1 and AVB2, mdio nodes will be needed to describe the connections, and each mdio node will need to contain these two properties instead. This will make the #address-cells and #size-cells described in the base SoC include file redundant and they will produce warnings, remove them. In an effort to keep all three AVB nodes style consistent add an mdio node to AVB0 already described and rename the phy node to better describe the PHY that is connected to AVB0 before adding more PHYs. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250107160127.528933-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 21 ++++++++++++------- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 6 ------ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 18fd52f55de5..f3a744e17d48 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -200,17 +200,22 @@ &avb0 { pinctrl-0 = <&avb0_pins>; pinctrl-names = "default"; - phy-handle = <&phy0>; + phy-handle = <&avb0_phy>; tx-internal-delay-ps = <2000>; status = "okay"; - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + avb0_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index d0c01c0fdda2..a7f100f2f4f0 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -793,8 +793,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -842,8 +840,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -891,8 +887,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 2>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; From d04079e0cadbfd95d1c108c8e60d71f15ff1a1f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 7 Jan 2025 17:01:27 +0100 Subject: [PATCH 04/34] arm64: dts: renesas: gray-hawk-single: Describe AVB1 and AVB2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe the two Marvell 88Q2110/QFN40 PHYs available on the R-Car V4M Gray Hawk single-board. The two PHYs are wired up on the board by default. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250107160127.528933-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index f3a744e17d48..55b187765932 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -46,6 +46,8 @@ serial0 = &hscif0; serial1 = &hscif2; ethernet0 = &avb0; + ethernet1 = &avb1; + ethernet2 = &avb2; }; can_transceiver0: can-phy0 { @@ -219,6 +221,48 @@ }; }; +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&avb1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&avb2_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb2_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + &can_clk { clock-frequency = <40000000>; }; @@ -563,6 +607,56 @@ }; }; + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + link { + groups = "avb1_link"; + bias-disable; + }; + + mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + link { + groups = "avb2_link"; + bias-disable; + }; + + mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + can_clk_pins: can-clk { groups = "can_clk"; function = "can_clk"; From b18ac9a805efdbc2e2720dded42b1ed26acadb24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 9 Jan 2025 13:54:32 +0100 Subject: [PATCH 05/34] arm64: dts: renesas: r8a779a0: Add FCPVX instances MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the FCPVX instances on R-Car V3U. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250109125433.2402045-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index fe6d97859e4a..44a32ab69277 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2338,6 +2338,42 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + + fcpvx2: fcp@fedc0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedc0000 0 0x200>; + clocks = <&cpg CPG_MOD 1102>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1102>; + iommus = <&ipmmu_vi1 26>; + }; + + fcpvx3: fcp@fedc8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedc8000 0 0x200>; + clocks = <&cpg CPG_MOD 1103>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1103>; + iommus = <&ipmmu_vi1 27>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x5000>; From 70403ebcff4265b25f9dbe1cc5d10ca551e28449 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 9 Jan 2025 13:54:33 +0100 Subject: [PATCH 06/34] arm64: dts: renesas: r8a779a0: Add VSPX instances MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the VSPX instances on R-Car V3U. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250109125433.2402045-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 44a32ab69277..905285b83f0c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2396,6 +2396,50 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + + vspx2: vsp@fede0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfede0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1030>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1030>; + + renesas,fcp = <&fcpvx2>; + }; + + vspx3: vsp@fede8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfede8000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1031>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1031>; + + renesas,fcp = <&fcpvx3>; + }; + csi40: csi2@feaa0000 { compatible = "renesas,r8a779a0-csi2"; reg = <0 0xfeaa0000 0 0x10000>; From d33e65dc3c4c9963b95b182f526480aaab9ce4a9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Jan 2025 12:05:09 +0100 Subject: [PATCH 07/34] arm64: dts: renesas: gray-hawk-single: Restore sort order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Alphabetical by label name. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/4f3e057b9a73d7ee7ff073f51bb9a4c30bdd0c84.1736506813.git.geert+renesas@glider.be --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 55b187765932..99bbb8a1b7b5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -282,25 +282,6 @@ }; }; -&dsi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - &csi40 { status = "okay"; @@ -341,6 +322,25 @@ }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; From 146a9b058ec780581f580b0de9bbc0264b59d701 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 15 Jan 2025 10:38:53 +0000 Subject: [PATCH 08/34] arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 200e9ea89193..133aa3272d3a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -175,6 +175,36 @@ status = "disabled"; }; + wdt1: watchdog@14400000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x14400000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x76>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@13000000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x77>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@13000400 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000400 0 0x400>; + clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x78>; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From db2bbe1e6c48f03ed1f5ac57f5614d02351dcb4c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 15 Jan 2025 10:38:54 +0000 Subject: [PATCH 09/34] arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog Enable WDT1 watchdog on RZ/G3E SMARC SoM platform. Signed-off-by: Biju Das Reviewed-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115103858.104709-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 6b583ae2ac52..f4ba050beb0d 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -26,3 +26,7 @@ &rtxin_clk { clock-frequency = <32768>; }; + +&wdt1 { + status = "okay"; +}; From f829a3e9cdaf3326f7c1c63badbf4625e77caa33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 15 Jan 2025 19:10:49 +0100 Subject: [PATCH 10/34] arm64: dts: renesas: r8a779h0: Add FCPVX instance MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device node for the FCPVX instance on R-Car V4M. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115181050.3728275-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index a7f100f2f4f0..cc2588f32c8d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1902,6 +1902,15 @@ resets = <&cpg 508>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; From 8e31f3b4fc294708d19a0dfeda65e82e63a4d9ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 15 Jan 2025 19:10:50 +0100 Subject: [PATCH 11/34] arm64: dts: renesas: r8a779h0: Add VSPX instance MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device node for the VSPX instance on R-Car V4M. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115181050.3728275-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index cc2588f32c8d..196b433bf82c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1921,6 +1921,17 @@ renesas,fcp = <&fcpvd0>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779h0"; reg = <0 0xfeb00000 0 0x40000>; From 7a847e34d531e8a66c302b2115032703ee4a3f32 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 15 Jan 2025 22:17:55 +0100 Subject: [PATCH 12/34] arm64: dts: renesas: eagle-function-expansion: Align GPIO hog name with bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warning: r8a77970-eagle-function-expansion.dtb: gpio@27: 'vin0_adv7612_en' does not match any of the regexes: '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250115211755.194219-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a77970-eagle-function-expansion.dtso | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso index 9450d8ac94cb..0c005660d8dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso @@ -70,7 +70,7 @@ gpio-controller; #gpio-cells = <2>; - vin0_adv7612_en { + vin0-adv7612-en-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-high; From f9b6e9976c3989e62861b84ab07a239bc9bc19a7 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 16 Jan 2025 23:47:52 +0900 Subject: [PATCH 13/34] arm64: dts: renesas: Add initial device tree for Yuridenki-Shokai Kakip board Add basic support for the Yuridenki-Shokai Kakip board based on R9A09G057H48, including: - Memory - OSTM0 - OSTM7 - Pin Control - Input clocks - SCIF - SDHI0 Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250116144752.1738574-5-iwamatsu@nigauri.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r9a09g057h48-kakip.dts | 136 ++++++++++++++++++ 2 files changed, 137 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 928635f2e76b..698f790bd425 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -149,6 +149,7 @@ dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb +dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts new file mode 100644 index 000000000000..d2586d278769 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for Yuridenki-Shokai the Kakip board + * + * Copyright (C) 2024 Nobuhiro Iwamatsu + */ + +/dts-v1/; + +#include +#include +#include "r9a09g057.dtsi" + +/ { + model = "Yuridenki-Shokai Kakip Board based on r9a09g057h48"; + compatible = "yuridenki,kakip", "renesas,r9a09g057h48", "renesas,r9a09g057"; + + aliases { + serial0 = &scif; + mmc0 = &sdhi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x1 0xF8000000>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + gpios = <&pinctrl RZV2H_GPIO(A, 0) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&ostm3 { + status = "okay"; +}; + +&ostm4 { + status = "okay"; +}; + +&ostm5 { + status = "okay"; +}; + +&ostm6 { + status = "okay"; +}; + +&ostm7 { + status = "okay"; +}; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_RXD", "SCIF_TXD"; + }; + + sd0-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd0_pwr_en"; + }; + + sdhi0_pins: sd0 { + sd0-clk { + pins = "SD0CLK"; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd0-data { + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd0-mux { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&scif { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi0>; + bus-width = <4>; + + status = "okay"; +}; From a4fdcbdcc4970f19f62658059294c2736e9f3776 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Jan 2025 12:13:08 +0100 Subject: [PATCH 14/34] arm64: dts: renesas: r8a779f0: Add labels for rswitch ports Introduce labels for each rswitch port in the form 'rswitch_portN'. Those can be used to access rswitch port nodes directly, which is going to be useful in reducing DT indentation slightly as well as in the DT /aliases node to reference the rswitch ports as ethernetN interfaces. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250118111344.361617-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 054498e54730..5457d527f9cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -974,15 +974,15 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + rswitch_port0: port@0 { reg = <0>; phys = <ð_serdes 0>; }; - port@1 { + rswitch_port1: port@1 { reg = <1>; phys = <ð_serdes 1>; }; - port@2 { + rswitch_port2: port@2 { reg = <2>; phys = <ð_serdes 2>; }; From d7801582dcb9497861f4bead495e8fd2d375081f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Jan 2025 12:13:09 +0100 Subject: [PATCH 15/34] arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles The r8a779f0.dtsi now contains labels for each rswitch port in the form 'rswitch_portN'. Use those to access rswitch ports and slightly reduce the depth of this board DT. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250118111344.361617-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779f0-spider-ethernet.dtsi | 87 +++++++++---------- 1 file changed, 42 insertions(+), 45 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi index 5d38669ed1ec..7d38ae5eeb6d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -42,61 +42,58 @@ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; pinctrl-names = "default"; status = "okay"; +}; - ethernet-ports { +&rswitch_port0 { + reg = <0>; + phy-handle = <&u101>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - phy-handle = <&u101>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u101: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - port@1 { + u101: ethernet-phy@1 { reg = <1>; - phy-handle = <&u201>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&rswitch_port1 { + reg = <1>; + phy-handle = <&u201>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; - mdio { - #address-cells = <1>; - #size-cells = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; - u201: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; + u201: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; }; - port@2 { - reg = <2>; - phy-handle = <&u301>; - phy-mode = "sgmii"; - phys = <ð_serdes 2>; + }; +}; + +&rswitch_port2 { + reg = <2>; + phy-handle = <&u301>; + phy-mode = "sgmii"; + phys = <ð_serdes 2>; - mdio { - #address-cells = <1>; - #size-cells = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; - u301: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; - }; - }; + u301: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; }; }; }; From b231d607b775c42e826c332b74b87dbb53413aaf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Jan 2025 12:13:10 +0100 Subject: [PATCH 16/34] arm64: dts: renesas: s4sk: Access rswitch ports via phandles The r8a779f0.dtsi now contains labels for each rswitch port in the form 'rswitch_portN'. Use those to access rswitch ports and slightly reduce the depth of this board DT. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250118111344.361617-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 71 +++++++++---------- 1 file changed, 33 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index 5d71d52f9c65..a4167dd955ae 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -179,53 +179,48 @@ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>; pinctrl-names = "default"; status = "okay"; +}; - ethernet-ports { +&rswitch_port0 { + reg = <0>; + phy-handle = <&ic99>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - phy-handle = <&ic99>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ic99: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - - port@1 { + ic99: ethernet-phy@1 { reg = <1>; - phy-handle = <&ic102>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ic102: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - - port@2 { - status = "disabled"; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; }; }; }; +&rswitch_port1 { + reg = <1>; + phy-handle = <&ic102>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ic102: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&rswitch_port2 { + status = "disabled"; +}; + &rwdt { timeout-sec = <60>; status = "okay"; From 1938912277f5170e61eae76d2249dc7d9c325484 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Jan 2025 12:13:11 +0100 Subject: [PATCH 17/34] arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitch The rswitch has three independent ports which each can act as a separate interface with its own MAC address. Describe DT aliases ethernet0, ethernet1, ethernet2 for each rswitch port in DT. This allows U-Boot to insert MAC addresses from its environment variables ethaddr/eth1addr/eth2addr into each rswitch port nodes, so Linux can read and use one unique MAC address for each rswitch port. Note that it is unlikely this would break existing rswitch driver operation in the Linux kernel, because as of right now, the rswitch driver already calls of_get_ethdev_address() for each port to read out the MAC address of each rswitch port DT node. If that is missing, it falls back to MAC address settings read from the hardware itself. If that also fails, it uses a random MAC address. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250118111344.361617-4-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi index 7d38ae5eeb6d..892729786d00 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -5,6 +5,14 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +/ { + aliases { + ethernet0 = &rswitch_port0; + ethernet1 = &rswitch_port1; + ethernet2 = &rswitch_port2; + }; +}; + ð_serdes { status = "okay"; }; From c7259ba78e36967ca124c8fe3b5d2300c814a02a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 18 Jan 2025 12:13:12 +0100 Subject: [PATCH 18/34] arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitch Each rswitch port TSNn has a dedicated MAC address assigned to it, so does AVB MAC. The MAC addresses for each rswitch port and AVB, four in total, are stored in the FPGA populated on the board and can be read out via I2C from bus i2c@e66e0000 address 0x70 offsets 0x58 for AVB and 0x60, 0x68, 0x70 for TSNn. There is no single MAC address assigned to the rswitch itself, there are three of them, one for each rswitch port. Instead of ethernet0 alias for rswitch itself, describe aliases ethernet0, ethernet1 for each enabled rswitch port. This allows U-Boot to insert MAC addresses from its environment variables ethaddr/eth1addr/eth2addr into each rswitch port nodes, so Linux can read and use one unique MAC address for each rswitch port. Note that it is unlikely this would break existing rswitch driver operation in the Linux kernel, because as of right now, the rswitch driver already calls of_get_ethdev_address() for each port to read out the MAC address of each rswitch port DT node. If that is missing, it falls back to MAC address settings read from the hardware itself. If that also fails, it uses a random MAC address. Fixes: 412f2224b3b6 ("arm64: dts: renesas: s4sk: Fix ethernet0 alias") Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250118111344.361617-5-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index a4167dd955ae..24ecdf6e8476 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -22,7 +22,8 @@ i2c5 = &i2c5; serial0 = &hscif0; serial1 = &hscif1; - ethernet0 = &rswitch; + ethernet0 = &rswitch_port0; + ethernet1 = &rswitch_port1; }; chosen { From 2f9f69188e5d1061bab9595edea8e89c7eff75ee Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Jan 2025 12:09:12 +0100 Subject: [PATCH 19/34] arm64: dts: renesas: r8a779g0: Restore sort order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Numerical by unit address, but grouped by type. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/ccd215c1146b84c085908e01966f7036be51afa8.1737370801.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 80 +++++++++++------------ 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 104f740d20d3..550e7dabd1da 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2171,6 +2171,24 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x7000>; @@ -2193,6 +2211,28 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779g0"; reg = <0 0xfeb00000 0 0x40000>; @@ -2453,46 +2493,6 @@ }; }; - fcpvx0: fcp@fedb0000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb0000 0 0x200>; - clocks = <&cpg CPG_MOD 1100>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1100>; - iommus = <&ipmmu_vi1 24>; - }; - - fcpvx1: fcp@fedb8000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb8000 0 0x200>; - clocks = <&cpg CPG_MOD 1101>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1101>; - iommus = <&ipmmu_vi1 25>; - }; - - vspx0: vsp@fedd0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 1028>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1028>; - - renesas,fcp = <&fcpvx0>; - }; - - vspx1: vsp@fedd8000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd8000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 1029>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1029>; - - renesas,fcp = <&fcpvx1>; - }; - prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 02760e35b5a62f0ca24e792817d720a2c8ddd409 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 20 Jan 2025 15:09:34 +0200 Subject: [PATCH 20/34] arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches There are different switches available on both the RZ/G3S SMARC Module and RZ SMARC Carrier II boards. These switches are used to route different SoC signals to different parts available on board. These switches are described in device trees through macros. These macros are set accordingly such that the resulted compiled dtb to describe the on-board switches states. The SCIF1 depends on the state of the SW_CONFIG3 and SW_OPT_MUX4 switches. SCIF1 can be enabled through a device tree overlay. To manage all switches in a unified state and allow users to configure the output device tree, add a file that contains all switch definitions and states. Commit prepares the code to enable SCIF1 on the RZ/G3S overlay. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250120130936.1080069-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 20 +----------- .../boot/dts/renesas/rzg3s-smarc-switches.h | 32 +++++++++++++++++++ 2 files changed, 33 insertions(+), 19 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a7..39845faec894 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -9,25 +9,7 @@ #include #include -/* - * On-board switches' states: - * @SW_OFF: switch's state is OFF - * @SW_ON: switch's state is ON - */ -#define SW_OFF 0 -#define SW_ON 1 - -/* - * SW_CONFIG[x] switches' states: - * @SW_CONFIG2: - * SW_OFF - SD0 is connected to eMMC - * SW_ON - SD0 is connected to uSD0 card - * @SW_CONFIG3: - * SW_OFF - SD2 is connected to SoC - * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - */ -#define SW_CONFIG2 SW_OFF -#define SW_CONFIG3 SW_ON +#include "rzg3s-smarc-switches.h" / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h new file mode 100644 index 000000000000..5c27c043afef --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II + * boards. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __RZG3S_SMARC_SWITCHES_H__ +#define __RZG3S_SMARC_SWITCHES_H__ + +/* + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON + */ +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_OFF +#define SW_CONFIG3 SW_ON + +#endif /* __RZG3S_SMARC_SWITCHES_H__ */ From ec32d57b4bbf27d91c55c7a258bdb87690993ea6 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 20 Jan 2025 15:09:35 +0200 Subject: [PATCH 21/34] arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 Enable SCIF3. It is routed to the SER1_UART interface on the RZ SMARC Carrier II board. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250120130936.1080069-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 81b4ffd1417d..0851e0b7ed40 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,7 @@ / { aliases { i2c0 = &i2c0; + serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -162,6 +163,11 @@ ; /* TXD */ }; + scif3_pins: scif3 { + pinmux = , /* RXD */ + ; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -208,6 +214,12 @@ status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; From cc018b98a9bf47c06bc985632a7ed9291decb965 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 20 Jan 2025 15:09:36 +0200 Subject: [PATCH 22/34] arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 Add a DT overlay for SCIF1 (of the Renesas RZ/G3S SoC) routed through the PMOD1_3A interface available on the Renesas RZ SMARC Carrier II board. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250120130936.1080069-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 ++ .../r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 +++++++++++++++++++ .../boot/dts/renesas/rzg3s-smarc-switches.h | 8 ++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 1 + 4 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 698f790bd425..c81d0f7f528a 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -143,6 +143,9 @@ r9a07g054l2-smarc-cru-csi-ov5645-dtbs := r9a07g054l2-smarc.dtb r9a07g054l2-smarc dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc-cru-csi-ov5645.dtb dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo +r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo +dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso new file mode 100644 index 000000000000..4a81e3a3c8bd --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC Carrier II EVK + * +--------------------------------------------+ + * |PMOD1_3A (PMOD1 PIN HEADER) | + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | + * | GND (pin5) (pin11) GND | + * | PWR_PMOD1 (pin6) (pin12) GND | + * +--------------------------------------------+ + * + * The following switches should be set as follows for SCIF1: + * - SW_CONFIG2: ON + * - SW_OPT_MUX4: ON + */ + +/dts-v1/; +/plugin/; + +#include +#include "rzg3s-smarc-switches.h" + +&pinctrl { + scif1_pins: scif1-pins { + pinmux = , /* TXD */ + , /* RXD */ + , /* CTS# */ + ; /* RTS# */ + }; +}; + +#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON +&scif1 { + pinctrl-names = "default"; + pinctrl-0 = <&scif1_pins>; + uart-has-rtscts; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h index 5c27c043afef..bbf908a5322c 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -29,4 +29,12 @@ #define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON +/* + * SW_OPT_MUX[x] switches' states: + * @SW_OPT_MUX4: + * SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART + * SW_ON - The SMARC SER0 signals are routed to PMOD1 + */ +#define SW_OPT_MUX4 SW_ON + #endif /* __RZG3S_SMARC_SWITCHES_H__ */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 0851e0b7ed40..5e044a4d0234 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,7 @@ / { aliases { i2c0 = &i2c0; + serial0 = &scif1; serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; From ab419f5b4a163707ff51eb74affdf32bb1c5ebd3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 23 Jan 2025 17:37:10 +0100 Subject: [PATCH 23/34] arm64: dts: renesas: r8a779f0: Disable rswitch ports by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Renesas Ethernet Switch has three independent ports. Each port can act as a separate interface, and can be enabled or disabled independently. Currently all ports are enabled by default, hence board DTS files that enable the switch must disable all unused ports explicitly. Disable all ports by default, and explicitly enable ports that are used, next to their configuration. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Reviewed-by: Marek Vasut Link: https://lore.kernel.org/c4688de8e3289ad82c2cd85f0893eac660ac8890.1737649969.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi | 3 +++ arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 3 +++ arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 6 ++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi index 892729786d00..ad2b0398d354 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -57,6 +57,7 @@ phy-handle = <&u101>; phy-mode = "sgmii"; phys = <ð_serdes 0>; + status = "okay"; mdio { #address-cells = <1>; @@ -75,6 +76,7 @@ phy-handle = <&u201>; phy-mode = "sgmii"; phys = <ð_serdes 1>; + status = "okay"; mdio { #address-cells = <1>; @@ -93,6 +95,7 @@ phy-handle = <&u301>; phy-mode = "sgmii"; phys = <ð_serdes 2>; + status = "okay"; mdio { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 5457d527f9cd..fdc466b84d51 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -977,14 +977,17 @@ rswitch_port0: port@0 { reg = <0>; phys = <ð_serdes 0>; + status = "disabled"; }; rswitch_port1: port@1 { reg = <1>; phys = <ð_serdes 1>; + status = "disabled"; }; rswitch_port2: port@2 { reg = <2>; phys = <ð_serdes 2>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index 24ecdf6e8476..df652e7b85c9 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -187,6 +187,7 @@ phy-handle = <&ic99>; phy-mode = "sgmii"; phys = <ð_serdes 0>; + status = "okay"; mdio { #address-cells = <1>; @@ -205,6 +206,7 @@ phy-handle = <&ic102>; phy-mode = "sgmii"; phys = <ð_serdes 1>; + status = "okay"; mdio { #address-cells = <1>; @@ -218,10 +220,6 @@ }; }; -&rswitch_port2 { - status = "disabled"; -}; - &rwdt { timeout-sec = <60>; status = "okay"; From 495af7647560c2b3a9c3107ea81dfd7d7c8a38c0 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 23 Jan 2025 18:05:06 +0100 Subject: [PATCH 24/34] arm64: dts: renesas: r9a08g045: Enable SYS node Enable the System Controller. It is needed for SoC identification. Signed-off-by: Claudiu Beznea Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250123170508.13578-8-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index a9b98db9ef95..d1e228b439df 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -443,7 +443,6 @@ ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; - status = "disabled"; }; pinctrl: pinctrl@11030000 { From 13e9b03263dcdc760aa65c4298271746b180f113 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Thu, 23 Jan 2025 18:05:07 +0100 Subject: [PATCH 25/34] arm64: dts: renesas: r9a09g047: Add SYS node Add a node for the System Controller to the RZ/G3E (R9A09G047) SoC DTSI, as it is also required for SoC identification. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250123170508.13578-9-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 133aa3272d3a..c93aa16d0a6e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -154,6 +154,13 @@ #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + scif0: serial@11c01400 { compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; From 0c507d15f09d72aecebd98deaa45029a2a0d8eef Mon Sep 17 00:00:00 2001 From: John Madieu Date: Thu, 23 Jan 2025 18:05:08 +0100 Subject: [PATCH 26/34] arm64: dts: renesas: r9a09g057: Enable SYS node SoC identification needs the System Controller. Enable it. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250123170508.13578-10-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1c550b22b164..f7a2f8ca864f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -249,7 +249,6 @@ reg = <0 0x10430000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; resets = <&cpg 0x30>; - status = "disabled"; }; ostm0: timer@11800000 { From b6f4b126b2471211f35720d8e976b65044e13020 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 28 Jan 2025 16:56:16 +0200 Subject: [PATCH 27/34] arm64: dts: renesas: r9a08g045: Add OPP table Add OPP table for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250128145616.2691841-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index d1e228b439df..0364f89776e6 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -28,6 +28,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-137500000 { + opp-hz = /bits/ 64 <137500000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -40,6 +67,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From e58ada2870cca12ee19c2dde5925fa9bf8a5f86b Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 31 Jan 2025 10:58:00 +0100 Subject: [PATCH 28/34] arm64: dts: renesas: Add initial support for MYIR Remi Pi Add basic support for the MYIR Remi Pi (based on r9a07g044l2): - UART, - I2C, - eMMC, - USB host, - HDMI output, - Ethernet. Signed-off-by: Julien Massot Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250131-myir-remi-pi-v3-2-2dda53e79291@collabora.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r9a07g044l2-remi-pi.dts | 339 ++++++++++++++++++ 2 files changed, 340 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index c81d0f7f528a..d25e665ee4bf 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts new file mode 100644 index 000000000000..3267e7b75b58 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the MYIR Remi Pi + * + * Copyright (C) 2022 MYIR Electronics Corp. + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; + +#include +#include + +#include "r9a07g044l2.dtsi" + +/ { + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + + mmc0 = &sdhi0; + + serial0 = &scif0; + serial4 = &scif4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&i2c1>; + + port { + hdmi_con: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + remote-endpoint = <<8912_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&gpu { + mali-supply = <®_1p1v>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + clock-frequency = <400000>; + status = "okay"; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8912_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&mtu3 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif4_pins: scif4 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + sdhi0_pins: sd0 { + sd0-ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0-data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0-rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; From 35a1c35e0a9d0e560a1369b801dd54efc7600101 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 3 Feb 2025 05:47:19 +0000 Subject: [PATCH 29/34] arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for capture Current ulcb/kf of -mix+split.dtsi is using TDM Split Mode, but only for playback. Use TDM Split Mode on capture too. Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/875xlrshp5.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- .../ulcb-kf-audio-graph-card-mix+split.dtsi | 73 ++++++++++++++++--- .../ulcb-kf-audio-graph-card2-mix+split.dtsi | 66 ++++++++++++++--- .../ulcb-kf-simple-audio-card-mix+split.dtsi | 53 ++++++++++++-- 3 files changed, 166 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi index 8ae6af1af094..4caa0281a687 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU3 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { sound_card_kf: expand-sound { @@ -35,13 +39,18 @@ routing = "pcm3168a Playback", "DAI2 Playback", "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; dais = <&snd_kf1 /* (C) CPU2 */ &snd_kf2 /* (D) CPU3 */ &snd_kf3 /* (E) CPU4 */ &snd_kf4 /* (F) CPU5 */ - &snd_kf5 /* (G) GPU6 */ + &snd_kf5 /* (G) CPU6 */ + &snd_kf6 /* (H) CPU7 */ + &snd_kf7 /* (I) CPU8 */ >; }; }; @@ -50,7 +59,9 @@ ports { #address-cells = <1>; #size-cells = <0>; + mclk-fs = <512>; + prefix = "pcm3168a"; /* * (Y) PCM3168A-p @@ -59,7 +70,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - prefix = "pcm3168a"; convert-channels = <8>; /* to 8ch TDM */ /* (C) CPU2 -> (Y) PCM3168A-p */ @@ -91,10 +101,28 @@ * (Z) PCM3168A-c */ port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + + convert-channels = <6>; /* to 6ch TDM */ + /* (G) CPU6 <- PCM3168A-c */ - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; + pcm3168a_endpoint_c1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_pcm3168a_capture1>; + clocks = <&clksndsel>; + }; + /* (H) CPU7 <- PCM3168A-c */ + pcm3168a_endpoint_c2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_pcm3168a_capture2>; + clocks = <&clksndsel>; + }; + /* (I) CPU8 <- PCM3168A-c */ + pcm3168a_endpoint_c3: endpoint@2 { + reg = <2>; + remote-endpoint = <&rsnd_for_pcm3168a_capture3>; clocks = <&clksndsel>; }; }; @@ -160,12 +188,35 @@ */ snd_kf5: port@6 { reg = <6>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; + rsnd_for_pcm3168a_capture1: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c1>; bitclock-master; frame-master; - dai-tdm-slot-num = <6>; - capture = <&ssi4>; + capture = <&ssiu40 &ssi4>; + }; + }; + /* + * (H) CPU7 + */ + snd_kf6: port@7 { + reg = <7>; + rsnd_for_pcm3168a_capture2: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c2>; + bitclock-master; + frame-master; + capture = <&ssiu41 &ssi4>; + }; + }; + /* + * (I) CPU8 + */ + snd_kf7: port@8 { + reg = <8>; + rsnd_for_pcm3168a_capture3: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c3>; + bitclock-master; + frame-master; + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi index 4cf632bc4621..67a0057a3383 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { sound_card_kf: expand-sound { @@ -36,19 +40,25 @@ "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", "pcm3168a Playback", "DAI5 Playback", - "DAI6 Capture", "pcm3168a Capture"; + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; links = <&fe_c /* (C) CPU2 */ &fe_d /* (D) CPU3 */ &fe_e /* (E) CPU4 */ &fe_f /* (F) CPU5 */ - &rsnd_g /* (G) CPU6 */ + &fe_g /* (G) CPU6 */ + &fe_h /* (H) CPU7 */ + &fe_i /* (I) CPU8 */ &be_y /* (Y) PCM3168A-p */ + &be_z /* (Z) PCM3168A-c */ >; - dpcm { + dpcm: dpcm { #address-cells = <1>; #size-cells = <0>; + non-supplier; ports@0 { #address-cells = <1>; @@ -62,21 +72,32 @@ * (D) CPU3 * (E) CPU4 * (F) CPU5 + * (G) CPU6 + * (H) CPU7 + * (I) CPU8 */ fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; + + fe_g: port@6 { reg = <6>; fe_g_ep: endpoint { remote-endpoint = <&rsnd_g_ep>; }; }; + fe_h: port@7 { reg = <7>; fe_h_ep: endpoint { remote-endpoint = <&rsnd_h_ep>; }; }; + fe_i: port@8 { reg = <8>; fe_i_ep: endpoint { remote-endpoint = <&rsnd_i_ep>; }; }; }; ports@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; /* * BE * * (Y) PCM3168A-p + * (Z) PCM3168A-c */ - be_y: port { be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + be_y: port@0 { reg = <0>; be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + be_z: port@1 { reg = <1>; be_z_ep: endpoint { remote-endpoint = <&pcm3168a_z_ep>; }; }; }; }; }; @@ -106,8 +127,9 @@ */ port@1 { reg = <1>; + convert-channels = <6>; /* to 6ch TDM */ pcm3168a_z_ep: endpoint { - remote-endpoint = <&rsnd_g_ep>; + remote-endpoint = <&be_z_ep>; clocks = <&clksndsel>; }; }; @@ -171,13 +193,37 @@ /* * (G) CPU6 */ - rsnd_g: port@6 { + port@6 { reg = <6>; rsnd_g_ep: endpoint { - remote-endpoint = <&pcm3168a_z_ep>; + remote-endpoint = <&fe_g_ep>; bitclock-master; frame-master; - capture = <&ssi4>; + capture = <&ssiu40 &ssi4>; + }; + }; + /* + * (H) CPU7 + */ + port@7 { + reg = <7>; + rsnd_h_ep: endpoint { + remote-endpoint = <&fe_h_ep>; + bitclock-master; + frame-master; + capture = <&ssiu41 &ssi4>; + }; + }; + /* + * (I) CPU8 + */ + port@8 { + reg = <8>; + rsnd_i_ep: endpoint { + remote-endpoint = <&fe_i_ep>; + bitclock-master; + frame-master; + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi index f01d91aaadf3..fd75801c329e 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { @@ -39,7 +43,10 @@ simple-audio-card,routing = "pcm3168a Playback", "DAI2 Playback", "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; simple-audio-card,dai-link@0 { #address-cells = <1>; @@ -88,15 +95,39 @@ }; simple-audio-card,dai-link@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + convert-channels = <6>; /* to 6ch TDM */ + /* * (G) CPU6 */ - cpu { + cpu@0 { + reg = <0>; bitclock-master; frame-master; sound-dai = <&rcar_sound 6>; }; + /* + * (H) CPU7 + */ + cpu@1 { + reg = <1>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 7>; + }; + /* + * (I) CPU8 + */ + cpu@2 { + reg = <2>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 8>; + }; + /* * (Z) PCM3168A-c */ @@ -151,7 +182,19 @@ * (G) CPU6 */ dai6 { - capture = <&ssi4>; + capture = <&ssiu40 &ssi4>; + }; + /* + * (H) CPU7 + */ + dai7 { + capture = <&ssiu41 &ssi4>; + }; + /* + * (I) CPU8 + */ + dai8 { + capture = <&ssiu42 &ssi4>; }; }; }; From 44a4951ffffe3663474547d1d72e88bea5420969 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 5 Feb 2025 11:33:11 +0100 Subject: [PATCH 30/34] arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line orders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The symbolic names for the line-orders are now available in . Switch to them instead of using their numerical values. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250205103311.668768-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi index 9017c4475a7c..a5d1c1008e7e 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi @@ -21,7 +21,9 @@ bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3>; - line-orders = <0 3 0>; + line-orders = ; remote-endpoint = <&max96712_out0>; }; }; @@ -42,7 +44,9 @@ bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3>; - line-orders = <0 3 0>; + line-orders = ; remote-endpoint = <&max96712_out1>; }; }; From f1a1268572cce15028c15d0faad37252a09ae06d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Feb 2025 19:05:04 +0100 Subject: [PATCH 31/34] ARM: dts: renesas: rcar-gen2: Add boot phase tags bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas R-Car Gen2 SoCs. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250209180616.160253-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7790-lager.dts | 1 + arch/arm/boot/dts/renesas/r8a7790-stout.dts | 1 + arch/arm/boot/dts/renesas/r8a7790.dtsi | 7 +++++++ arch/arm/boot/dts/renesas/r8a7791-koelsch.dts | 1 + arch/arm/boot/dts/renesas/r8a7791-porter.dts | 1 + arch/arm/boot/dts/renesas/r8a7791.dtsi | 7 +++++++ arch/arm/boot/dts/renesas/r8a7792-blanche.dts | 1 + arch/arm/boot/dts/renesas/r8a7792-wheat.dts | 1 + arch/arm/boot/dts/renesas/r8a7792.dtsi | 6 ++++++ arch/arm/boot/dts/renesas/r8a7793-gose.dts | 1 + arch/arm/boot/dts/renesas/r8a7793.dtsi | 7 +++++++ arch/arm/boot/dts/renesas/r8a7794-alt.dts | 1 + arch/arm/boot/dts/renesas/r8a7794-silk.dts | 1 + arch/arm/boot/dts/renesas/r8a7794.dtsi | 7 +++++++ 14 files changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 3bce5876a9d8..4f002aa7fbaf 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -754,6 +754,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts index d7c0a9574ce8..b1e20579e071 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -268,6 +268,7 @@ &scifa0 { pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index f746f0b9e686..4f97c09dbc9f 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -227,6 +227,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -265,6 +266,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -374,6 +376,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -395,6 +398,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -412,6 +416,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7790-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1948,6 +1953,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -2018,5 +2024,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index e4e1d9c98c61..e9f90fa44d55 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -679,6 +679,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index 08381498350a..f518eadd8b9c 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -312,6 +312,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index e57567adff55..5023b41c28b3 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -125,6 +125,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -152,6 +153,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -291,6 +293,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -312,6 +315,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -323,6 +327,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7791-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1875,6 +1880,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1945,5 +1951,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts index a3986076d8e3..23ec0f8a6651 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -301,6 +301,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts index bfc780f7e396..93bd81723c8f 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts @@ -183,6 +183,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 08cbe6c13cee..7513afc1c958 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -82,6 +82,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; lbsc: bus { @@ -109,6 +110,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -308,6 +310,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -318,6 +321,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -329,6 +333,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7792-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -947,6 +952,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 2c05d7c2b377..45b267ec2679 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -642,6 +642,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index e48e43cc6b03..fc6d3bcca296 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -117,6 +117,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -137,6 +138,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -276,6 +278,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; /* Special CPG clocks */ @@ -287,6 +290,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -298,6 +302,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7793-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1454,6 +1459,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1524,5 +1530,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index f70e26aa83a0..3f06a7f67d62 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -479,6 +479,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts index 2a0819311a3c..342825605768 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -394,6 +394,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index bc16c896c0f9..92010d09f6c4 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -99,6 +99,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -119,6 +120,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -243,6 +245,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -253,6 +256,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -264,6 +268,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7794-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1440,6 +1445,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1491,5 +1497,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; From 399f14ff6625cbfb666c4372a469714f840f7df3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Feb 2025 19:05:05 +0100 Subject: [PATCH 32/34] arm64: dts: renesas: rcar: Add boot phase tags bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas R-Car SoCs. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250209180616.160253-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/condor-common.dtsi | 1 + arch/arm64/boot/dts/renesas/draak.dtsi | 1 + arch/arm64/boot/dts/renesas/ebisu.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 1 + arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 1 + arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 1 + arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 + arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 + arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi | 1 + 25 files changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 375a56b20f26..a10584150571 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -544,6 +544,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 05712cd96d28..380b857fd273 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -695,6 +695,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ab8283656660..4f38b01ae18d 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -786,6 +786,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 96f3b5fe7e92..6ee9cdeb5a3a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -292,6 +292,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -299,6 +300,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -347,6 +349,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -485,6 +488,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -565,11 +569,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7795-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -3398,6 +3404,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ee80f52dc7cf..a323ac47ca70 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7796-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2996,6 +3003,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 3b9066043a71..49f6d31c5903 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77961"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77961-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2817,6 +2824,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 557bdf8fab17..136a22ca50b7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -143,6 +143,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -150,6 +151,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -182,6 +184,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -320,6 +324,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -400,11 +405,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77965-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2828,6 +2835,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 32f07aa27316..8b594e9e9dc1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -409,6 +409,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 118e77f4477e..445f5dd7c983 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -296,6 +296,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 38145fd6acf0..01744496805c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -60,6 +60,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -67,6 +68,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -91,6 +93,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -200,6 +203,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77970"; reg = <0 0xe6060000 0 0x504>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -280,11 +284,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77970-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1196,6 +1202,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index b409a8d1737e..c2692d6fd00d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -282,6 +282,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 55a6c622f873..f7e506ad7a21 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -80,6 +80,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -87,6 +88,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -120,6 +122,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -229,6 +232,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -309,11 +313,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77980-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1579,6 +1585,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 50fbf7251665..6b8742045836 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -122,6 +122,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -153,6 +154,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -276,6 +279,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; i2c_dvfs: i2c@e60b0000 { @@ -372,11 +376,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77990-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2121,6 +2127,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f0828a4675b..b66cd7c90d53 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -65,6 +65,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -86,6 +87,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -209,6 +212,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -289,11 +293,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77995-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1448,6 +1454,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index e8c8fca48b69..0916fd57d1f1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -348,6 +348,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 905285b83f0c..f1613bfd1632 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -47,6 +47,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -54,6 +55,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a76 { @@ -71,6 +73,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -93,6 +97,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6058180 { @@ -331,11 +336,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779a0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2973,6 +2980,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index e03baefb6a98..1781bb79a619 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -101,6 +101,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index fdc466b84d51..b496495c59a6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -253,6 +253,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -260,6 +261,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -296,6 +298,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -315,6 +319,7 @@ compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -463,11 +468,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779f0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1283,6 +1290,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index df652e7b85c9..67b18f2bffbd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -68,6 +68,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 550e7dabd1da..1760720b7128 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -166,6 +166,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -173,6 +174,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -215,6 +217,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -237,6 +241,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, <0 0xe6068000 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -452,11 +457,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779g0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2496,6 +2503,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 99bbb8a1b7b5..4d890e0617af 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -361,6 +361,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 196b433bf82c..8524a1e7205e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -138,6 +138,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr-clk { @@ -145,6 +146,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -180,6 +182,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -201,6 +205,7 @@ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -401,11 +406,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779h0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2158,6 +2165,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 06c7e9746304..68971c870d17 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -940,6 +940,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0c58d816c375..fcab957b54f7 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -448,6 +448,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index f24814d7c924..b4024e85ae5a 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -201,6 +201,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; From 624b2a23d46abc5ca5f336598dfe8c339a964aae Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 9 Feb 2025 19:05:06 +0100 Subject: [PATCH 33/34] arm64: dts: renesas: rzg2: Add boot phase tags bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas RZ/G2 SoCs. All SoC require CPG clock and its input clock, RST Reset, PFC pin control and PRR ID register access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains these IP. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250209180616.160253-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 1 + arch/arm64/boot/dts/renesas/hihope-common.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 8 ++++++++ 7 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 43f88c199b78..1489bc8d2f4e 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -282,6 +282,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 659ae1fed2fa..4e78139d52f6 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -289,6 +289,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f065ee90649a..c8b87aed92a3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -215,6 +215,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -222,6 +223,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -262,6 +264,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -400,6 +404,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -480,11 +485,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774a1-rst"; reg = <0 0xe6160000 0 0x018c>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2785,6 +2792,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 117cb6950f91..f2fc2a2035a1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -108,6 +108,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -115,6 +116,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -146,6 +148,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -284,6 +288,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774b1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -364,11 +369,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774b1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2661,6 +2668,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index b78dbd807d15..57a281fc4977 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -378,6 +378,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 522e20924e94..530ffd29cf13 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -107,6 +107,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -138,6 +139,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -261,6 +264,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774c0"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -341,11 +345,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774c0-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1957,6 +1963,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f845ca604de0..e4dbda8c34d9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -277,6 +277,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -284,6 +285,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -326,6 +328,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -464,6 +468,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -544,11 +549,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774e1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2917,6 +2924,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; From 5f7ebb81112c3f50ffbb8e576e4d35cedd8aabb1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 14 Feb 2025 10:42:03 +0100 Subject: [PATCH 34/34] ARM: dts: renesas: r9a06g032: Fix UART dma channel order make dtbs_check: arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: serial@50000000: dma-names:0: 'tx' was expected from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: serial@50000000: dma-names:1: 'rx' was expected from schema $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml# ... The DT bindings specify a fixed order of the channels in the dmas and dma-names properties, while the Linux driver does not care. Get rid of the warnings by changing the order in the DTS to match the bindings. Signed-off-by: Geert Uytterhoeven Reviewed-by: Miquel Raynal Link: https://lore.kernel.org/bcb604ad6e567de4e0410756ba840c82a32ff7d3.1739525488.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 7548291c8d7e..87e03446fb4d 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -211,8 +211,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -224,8 +224,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -237,8 +237,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -250,8 +250,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,8 +263,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; + dma-names = "tx", "rx"; status = "disabled"; };