mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor

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commit d4b803c559 upstream.

According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not available. In this case we use the
SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities.

This commit is based on the work done by Marcin Wojtas<mw@semihalf.com>

Fixes: 5491ce3f79 ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Luis Henriques <luis.henriques@canonical.com>

...

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Gregory CLEMENT 2015-01-29 12:36:24 +01:00 • committed by Luis Henriques

parent 2234e863e9

commit c930c075f1

1 changed files with 17 additions and 0 deletions

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drivers/mmc/host/sdhci-pxav3.c

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