arm64: dts: qcom: sm8650: add cpu interconnect nodes

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Add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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Neil Armstrong 2025-02-11 13:56:38 +01:00 • committed by Bjorn Andersson

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commit c9658c3963

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arch/arm64/boot/dts/qcom/sm8650.dtsi

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