dmaengine: dw: fix a typo for bitfields of CTL_LO

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The offset of SINC should be 9, not 7, here fix this
typo.

Signed-off-by: Jie Yang <yang.jie@intel.com>
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

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Jie Yang 2016-01-07 08:39:33 +08:00 • committed by Vinod Koul

parent 92e963f50f

commit c9784a4673

1 changed files with 1 additions and 1 deletions

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drivers/dma/dw/regs.h

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